NS32FX161-15 Datasheet, PDF (28/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand Section
3 5 5 1) Upon receiving it the Slave Processor decodes it
and at this point both the CPU and the Slave Processor are
aware of the number of operands to be transferred and their
sizes The Operation Word is swapped on the Data Bus
that is bits 0 – 7 appear on pins AD8–AD15 and bits 8–15
appear on pins AD0–AD7
Using the Address Mode fields within the Operation Word
the CPU starts fetching operands and issuing them to the
Slave Processor To do so it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction Since the CPU is solely responsible
for memory accesses these extensions are not sent to the
Slave Processor The Status Code applied is 1101 (Transfer
Slave Processor Operand Section 3 5 5 1)
After the CPU has issued the last operand the Slave Proc-
essor starts the actual execution of the instruction Upon
completion it will signal the CPU by pulsing SPC low
While the Slave Processor is executing the instruction the
CPU is free to prefetch instructions into its queue If it fills
the queue before the Slave Processor finishes the CPU will
wait applying Status Code 0011 (Waiting for Slave)
Upon receiving the pulse on SPC the CPU uses SPC to
read a Status Word from the Slave Processor applying
Status Code 1110 (Read Slave Status) This word has the
format shown in Figure 3-3 If the Q-bit (‘‘Quit’’ Bit 0) is set
this indicates that an error was detected by the Slave Proc-
essor The CPU will not continue the protocol but will imme-
Step
1
2
3
4
5
6
7
Status Combinations
Send ID (ID) Code 1111
Xfer Operand (OP) Code 1101
Read Status (ST) Code 1110
Status
ID
OP
OP
ST
OP
Action
CPU Sends ID Byte
CPU Sends Operation Word
CPU Sends Required Operands
Slave Starts Execution
CPU Pre-Fetches
Slave Pulses SPC Low
CPU Reads Status Word
(Trap Alter Flags )
CPU Reads Results (If Any)
FIGURE 3-2 Slave Processor Protocol
diately trap through the Slave vector in the Interrupt Table
Certain Slave Processor instructions cause CPU PSR bits to
be loaded from the Status Word
The last step in the protocol is for the CPU to read a result
if any and transfer it to the destination The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand)
3 1 3 2 Floating-Point Instructions
Table 3-1 gives the protocols followed for each Floating-
Point instruction The instructions are referenced by their
mnemonics For the bit encodings of each instruction see
Appendix A
Mnemonic
ADDf
SUBf
MULf
DIVf
Operand 1
Class
read f
read f
read f
read f
TABLE 3-1 Floating-Point Instruction Protocols
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
rmw f
f
f
rmw f
f
f
rmw f
f
f
rmw f
f
f
MOVf
read f
write f
f
NA
ABSf
read f
write f
f
NA
NEGf
read f
write f
f
NA
CMPf
read f
read f
f
f
FLOORfi
read f
write i
f
NA
TRUNCfi
read f
write i
f
NA
ROUNDfi
read f
write i
f
NA
MOVFL
read F
write L
F
NA
MOVLF
read L
write F
L
NA
MOVif
read i
write f
i
NA
LFSR
SFSR
read D
NA
D
NA
NA
write D
NA
NA
POLYf
read f
read f
f
DOTf
read f
read f
f
SCALBf
read f
rmw f
f
LOGBf
read f
write f
f
Notes
D e Double Word
i e Integer size (B W D) specified in mnemonic
f e Floating-Point type (F L) specified in mnemonic
N A e Not Applicable to this instruction
f
f
f
NA
Returned Value
Type and Dest
f to Op 2
f to Op 2
f to Op 2
f to Op 2
f to Op 2
f to Op 2
f to Op 2
NA
i to Op 2
i to Op 2
i to Op 2
L to Op 2
F to Op 2
f to Op 2
NA
D to Op 2
f to F0
f to F0
f to Op 2
f to Op 2
PSR Bits
Affected
none
none
none
none
none
none
none
NZL
none
none
none
none
none
none
none
none
none
none
none
none
28