MC68HC11F1 Datasheet, PDF (66/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

PAMOD
0
0
1
1
Table 33 Pulse Accumulator Edge Control
PEDGE
0
1
0
1
Action on Clock
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
A one on PAI inhibits counting.
Bit 3 — Not implemented. Reads always return zero and writes have no effect.
Bits [2:0] — See 12.2 Timer Registers, page 63.
PACNT — Pulse Accumulator Count
$x027
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
U
U
U
U
U
U
U
U
U = Unaffected by reset
This eight-bit read/write register contains the count of external input events at the PAI input, or the ac-
cumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.
The counter is not affected by reset and can be read or written at any time. Counting is synchronized
to the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
MOTOROLA
66
MC68HC11F1/FC0
MC68HC11FTS/D