MC68HC11F1 Datasheet, PDF (27/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

CR[1:0] — COP Timer Rate Select
The COP system is driven by a constant frequency of E/2¹⁵. CR[1:0] specify an additional divide-by fac-
tor to arrive at the COP time-out rate.
Table 12 COP Watchdog Time-Out Periods
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
Tolerance
-0/+32.768 ms
-0/+16.384 ms
-0/+10.923 ms
-0/+8.192 ms
-0/+6.554 ms
-0/+5.461 ms
-0/+2¹⁵/E
CR[1:0] = 00
32.768 ms
16.384 ms
10.923 ms
8.192 ms
6.554 ms
5.461 ms
2¹⁵/E
CR[1:0] = 01
131.072 ms
65.536 ms
43.691 ms
32.768 ms
26.214 ms
21.845
2¹⁷/E
CR[1:0] = 10
524.288 ms
262.144 ms
174.763 ms
131.072 ms
104.858 ms
87.381 ms
2¹⁹/E
CR[1:0] = 11
2.097 s
1.049 s
699.051 ms
524.288 ms
419.430 ms
349.525 ms
2²¹/E
COPRST — Arm/Reset COP Timer Circuitry
$x03A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST to
reset the COP timer. Performing instructions between these two steps is possible provided both steps
are completed in the correct sequence before the timer times out.
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
RESET:
Bit 7
RBOOT
6
SMOD
5
MDA
4
3
2
IRV
PSEL3 PSEL2
0
1
Bits [7:4] — See 4.3 System Initialization Registers, page 20.
1
PSEL1
0
Bit 0
PSEL0
1
$x03C
PSEL[3:0] — Interrupt Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to have priority over other I-bit related sources.
Table 13 Highest Priority Interrupt Selection
PSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Interrupt Source Promoted
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
IRQ (External Pin)
Real-Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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