MC68HC11F1 Datasheet, PDF (18/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

4 Operating Modes and System Initialization
The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and
MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and
the address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control reg-
ister block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM.
RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both the
MC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers re-
side at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4-
Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and regis-
ters can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space.
RAM and control register locations are defined by the INIT register, which can be written only once with-
in the first 64 E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter.
If RAM and the control register block are mapped to the same boundary, the register block has priority
of the first 96 bytes.
In expanded and special test modes in the MC68HC11F1, EEPROM is located from $xE00 to $xFFF,
where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabled
by the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is located
from $FE00 to $FFFF.
4.1 Operating Modes
Bootstrap ROM resides at addresses $BF00–$BFFF, and is only available when the MCU operates in
special bootstrap operating mode. Operating modes are determined by the logic levels applied to the
MODB and MODA pins at reset.
In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address
or data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputs
only; each of the port C pins can be configured as input or output.
CAUTION
The MC68HC11FC0 must not be configured to boot in single-chip mode because
it has no internal ROM or EEPROM. Operation of the device in single-chip mode
will result in erratic behavior.
In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, and
port C is the data bus.
Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap
ROM. In this mode, the user can download a program into on-chip RAM through the serial communica-
tion interface (SCI).
Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal production
testing, but can support emulation and debugging during program development.
Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register.
Table 7 Hardware Mode Select Summary
Input Pins
MODB MODA
1
0
1
1
0
0
0
1
Mode Description
Single Chip
Expanded
Special Bootstrap
Special Test
Control Bits in HPRIO (Latched at Reset)
RBOOT
SMOD
MDA
0
0
0
0
0
1
1
1
0
0
1
1
MOTOROLA
18
MC68HC11F1/FC0
MC68HC11FTS/D