MC68HC11F1 Datasheet, PDF (22/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

INIT — RAM and I/O Mapping (MC68HC11F1 only)
Bit 7
6
5
4
RAM3 RAM2 RAM1 RAM0
RESET:
0
0
0
0
3
REG3
0
2
REG4
0
1
REG1
0
Bit 0
REG0
1
$x03D
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11F1 only. A diagram and bit
descriptions of the INIT register in the MC68HC11FC0 are provided elsewhere in
this section.
RAM[3:0] — Internal RAM Map Position
These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any four-
Kbyte boundary. Refer to Table 10.
REG[3:0] — 96-Byte Register Block Map Position
These bits determine bits the upper 4 bits of the register block and allow mapping of the register block
to any four-Kbyte boundary. Refer to Table 10.
Table 10 RAM and Register Mapping
RAM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0000-$03FF
$1000-$13FF
$2000-$23FF
$3000-$33FF
$4000-$43FF
$5000-$53FF
$6000-$63FF
$7000-$73FF
$8000-$83FF
$9000-$93FF
$A000-$A3FF
$B000-$B3FF
$C000-$C3FF
$D000-$D3FF
$E000-$E3FF
$F000-$F3FF
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0000-$005F
$1000-$105F
$2000-$205F
$3000-$305F
$4000-$405F
$5000-$505F
$6000-$605F
$7000-$705F
$8000-$805F
$9000-$905F
$A000-$A05F
$B000-$B05F
$C000-$C05F
$D000-$D05F
$E000-$E05F
$F000-$F05F
OPT2 — System Configuration Option Register 2
$x038
Bit 7
6
5
4
3
2
1
Bit 0
GWOM CWOM CLK4X LIRDV
—
SPRBYP
—
—
RESET
0
0
1
0
0
0
0
0
GWOM — Port G Wired-OR Mode Option
Refer to 7.8 Parallel I/O Registers, page 36.
MOTOROLA
22
MC68HC11F1/FC0
MC68HC11FTS/D