MC68HC11F1 Datasheet, PDF (36/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

PORTD — Port D Data Register
RESET:
Alternate
Function:
Bit 7
0
0
—
6
5
4
3
2
1
Bit 0
0
PD5
PD4
PD3
PD2
PD1
PD0
0
I
I
I
I
I
I
—
SS
SCK
MOSI
MISO
TxD
RxD
$x008
DDRD — Port D Data Direction Register
Bit 7
6
5
0
0
DDD5
RESET:
0
0
0
4
DDD4
0
3
DDD3
0
2
DDD2
0
1
DDD1
0
Bit 0
DDD0
0
$x009
For DDRx bits, 0 = input and 1 = output.
NOTE
When the SPI system is in slave mode, DDD5 has no meaning or effect. When the
SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an er-
ror detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI sys-
tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will be
inputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]
are expected to be outputs, those bits will be outputs only if the associated DDR
bits are set.
PORTE — Port E Data
$x00A
Bit 7
6
5
4
3
2
1
Bit 0
PE7¹
PE6
PE5
PE4²
PE3
PE2
PE1
PE0¹
RESET:
U
U
U
U
U
U
U
U
Alternate
Function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
NOTES:
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the 64-pin QFP version of the MC68HC11FC0 and will always read zero.
U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.
On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is not
present on the MC68HC11FC0.)
OPT2 — System Configuration Option Register 2
$x038
Bit 7
6
5
4
3
2
1
Bit 0
GWOM CWOM CLK4X LIRDV
—
SPRBYP
—
—
RESET
0
0
1
0
0
0
0
0
GWOM — Port G Wired-OR Mode Option
This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs
1 = Port G outputs act as open-drain outputs
MOTOROLA
36
MC68HC11F1/FC0
MC68HC11FTS/D