MC68HC11F1 Datasheet, PDF (61/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

OMx
0
0
1
1
Table 29 Output Compare Actions
OLx
Action Taken on Successful Compare
0 Timer disconnected from output pin logic
1 Toggle OCx output line
0 Clear OCx output line to zero
1 Set OCx output line to one
TCTL2 — Timer Control 2
Bit 7
6
EDG4B EDG4A
RESET:
0
0
5
EDG1B
0
4
EDG1A
0
3
EDG2B
0
2
EDG2A
0
1
EDG3B
0
Bit 0
EDG3A
0
$x021
EDGxB, EDGxA — Input Capture Edge Control
Each EDGxB, EDGxA pair determines the polarity of the input signal on the corresponding ICx that will
trigger an input capture, as shown in Table 30. IC4 functions only if the I4/O5 bit in the PACTL register
is set.
Table 30 Input Capture Configuration
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
TMSK1 — Timer Interrupt Mask 1
Bit 7
6
5
4
3
2
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
RESET:
0
0
0
0
0
0
1
Bit 0
IC2I
IC3I
0
0
$x022
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Each bit that is set in TMSK1 enables the
corresponding interrupt source.
OCxI — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL
is zero, I4/O5I is the output compare 5 interrupt enable bit.
ICxI — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
TFLG1 — Timer Interrupt Flag 1
$x023
Bit 7
6
5
4
3
2
1
Bit 0
OC1F
OC2F
OC3F
OC4F I4/O5F
IC1F
IC2F
IC3F
RESET:
0
0
0
0
0
0
0
0
Bits in TFLG1 are cleared by writing a one to the corresponding bit positions.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
61