MC68HC11F1 Datasheet, PDF (34/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

7.7 Port G
Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register
(DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded
modes. When any of these pins are not being used for chip selects, they can be used for general-pur-
pose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 reg-
ister.
NOTE
PG[1:0] are not available on the 64-pin MC68HC11FC0.
7.8 Parallel I/O Registers
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an “I” indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a “U”.
PORTA — Port A Data Register
Bit 7
6
5
PA7
PA6
PA5
RESET:
I
I
I
Alternate
Function:
PAI
OC2
OC3
And/or:
OC1
OC1
OC1
4
PA4
I
OC4
OC1
I = Indeterminate value
DDRA — Port A Data Direction Register
Bit 7
6
5
DDA7 DDA6 DDA5
RESET:
0
0
0
4
DDA4
0
For DDRx bits, 0 = input and 1 = output.
3
PA3
I
OC5/IC4
OC1
3
DDA3
0
2
PA2
I
IC1
—
2
DDA2
0
1
PA1
I
IC2
—
1
DDA1
0
Bit 0
PA0
I
IC3
—
Bit 0
DDA0
0
$x000
$x001
PORTG — Port G Data Register
Bit 7
6
5
4
3
PG7
PG6
PG5
PG4
PG3
RESET:
I
I
I
I
I
Alternate
Function:
CSPROG
CSGEN
CSIO1
CSIO2
2
PG2
I
1
PG1*
I
*These bits are not present on the 64-pin QFP version of the MC68HC11FC0.
I = Indeterminate value
Bit 0
PG0*
I
$x002
MOTOROLA
34
MC68HC11F1/FC0
MC68HC11FTS/D