MC68HC11F1 Datasheet, PDF (50/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

10.2 SPI Registers
SPCR — SPI Control Register
RESET:
Bit 7
SPIE
0
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
$x028
U = Unaffected by reset
SPIE — SPI Interrupt Enable
When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition code
register is one.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — SPI Enable
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and the
DDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Option for SPI Pins PD[5:2]
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device
has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between mas-
ter and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
1
2
3
4
5
6
7
8
SAMPLE INPUT
(CPHA = 0) DATA OUT
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 13 SPI Data Clock Timing Diagram
MOTOROLA
50
MC68HC11F1/FC0
MC68HC11FTS/D