MC68HC11F1 Datasheet, PDF (26/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

Vector Address
FFC0, C1
to
FFD4, D5
FFD6, D7
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
Table 11 Interrupt and Reset Vector Assignments
Interrupt Source
CCR Mask Local Mask
Reserved
SCI Serial System
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
SCI Receiver Overrun
SCI Receive Data Register Full
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real-Time Interrupt
IRQ
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
—
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
X Bit
None
None
None
None
None
—
TCIE
TIE
ILIE
RIE
RIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None
Flag Bit
—
TC
TDRE
IDLE
OR
RDRF
SPIF
PAIF
PAOVF
TOF
I4/O5F
OC4F
OC3F
OC2F
OC1F
IC3F
IC2F
IC1F
RTIF
None
None
None
None
None
None
None
5.2 Reset and Interrupt Registers
OPTION — System Configuration Options
RESET:
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
FCME*
0
1
CR1*
0
Bit 0
CR0*
0
$x039
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Bits [7:6], [4:2]
Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56.
IRQE — IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
MOTOROLA
26
MC68HC11F1/FC0
MC68HC11FTS/D