MC68HC11F1 Datasheet, PDF (59/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

12.2 Timer Registers
CFORC — Timer Force Compare
Bit 7
6
5
4
3
2
FOC1 FOC2 FOC3 FOC4 FOC5
0
RESET:
0
0
0
0
0
0
$x00B
1
Bit 0
0
0
0
0
FOCx — Force Output Compare x Action
0 = Not affected
1 = Output compare x action occurs, but OCxF flag bit is not set
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1M — Output Compare 1 Mask
Bit 7
6
5
4
3
2
1
Bit 0
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
0
0
0
RESET:
0
0
0
0
0
0
0
0
$x00C
Bits set in OC1M allow OC1 to output the corresponding OC1D bits in port A when a successful com-
pare event occurs.
OC1M[7:3] — Output Compare Masks
0 = Control of the corresponding port A pin is disabled
1 = Control of the corresponding port A pin is enabled
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1D — Output Compare 1 Data
Bit 7
6
5
4
3
2
1
Bit 0
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
0
0
0
RESET:
0
0
0
0
0
0
0
0
$x00D
OC1D[7:3] — Output Compare Data
Data in OC1Dx is output to port A bit x on successful OC1 compares if OC1Mx is set.
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
TCNT — Timer Count
$x00E
Bit 15
14
13
12
11
10
9
$x00F
Bit 7
6
5
4
3
2
1
RESET:
0
0
0
0
0
0
0
$x00E, $x00F
Bit 8
High
Bit 0
Low
0
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byte
to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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