MC68HC11F1 Datasheet, PDF (35/68 Pages) Motorola, Inc – Technical Summary 8-Bit Microcontroller

DDRG — Port G Data Direction Register
Bit 7
6
5
DDG7* DDG6 DDG5
RESET:
0
0
0
4
DDG4
0
3
DDG3
0
2
DDG2
0
1
DDG1
0
Bit 0
DDG0
0
$x003
* Following reset in expanded and test modes, PG7/CSPRG is configured as a program chip select, forcing the pin
to be an output pin, even though the value of the DDG7 bit remains zero.
For DDRx bits, 0 = input and 1 = output.
PORTB — Port B Data Register
Bit 7
6
5
4
3
2
PB7
PB6
PB5
PB4
PB3
PB2
RESET:
0
0
0
0
0
0
Alternate
Function:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
1
PB1
0
ADDR9
Bit 0
PB0
0
ADDR8
$x004
The reset state of port B is mode dependent. In single-chip or bootstrap modes, port B pins are general-
purpose outputs. In expanded and test modes, port B pins are high-order address outputs and PORTB
is not in the memory map.
PORTF — Port F Data Register
PF7
PF6
PF5
RESET:
0
0
0
Alternate
Function:
ADDR7
ADDR6
ADDR5
PF4
0
ADDR4
PF3
0
ADDR3
PF2
0
ADDR2
PF1
0
ADDR1
PF0
0
ADDR0
$x005
The reset state of port F is mode dependent. In single-chip or bootstrap modes, port F pins are general-
purpose outputs. In expanded and test modes, port F pins are low-order address outputs and PORTF
is not in the memory map.
PORTC — Port C Data Register
Bit 7
6
5
PC7
PC6
PC5
RESET:
I
I
I
Alternate
Function:
DATA7
DATA6
DATA5
4
PC4
I
DATA4
3
PC3
I
DATA3
2
PC2
I
DATA2
1
PC1
I
DATA1
Bit 0
PC0
I
DATA0
$x006
The reset state of port C is mode dependent. In single-chip and bootstrap modes, port C pins are high-
impedance inputs. In expanded or test modes, port C pins are data bus inputs/outputs and PORTC is
not in the memory map. The R/W signal is used to control the direction of data transfers.
DDRC — Port C Data Direction Register
Bit 7
6
5
DDC7 DDC6 DDC5
RESET:
0
0
0
4
DDC4
0
For DDRx bits, 0 = input and 1 = output.
3
DDC3
0
2
DDC2
0
1
DDC1
0
Bit 0
DDC0
0
$x007
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
35