M306V5ME-XXXSP Datasheet, PDF (88/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.11 Serial I/O
Serial I/O is configured as 4 unites: UART0, UART2, multi-master I²C-BUS interface 0, and multi-master
I²C-BUS interface 1.
2.11.1 UART0 and UART2
UART0 and UART2 each have an exclusive timer to generate a transfer clock, so they operate indepen-
dently of each other.
Figure 2.11.1 shows the block diagram of UART0 and UART2. Figures 2.11.2 and 2.11.3 show the block
diagram of the transmit/receive unit.
UARTi (i = 0 and 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016
and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a
few functions are different, UART0 and UART2 have almost the same functions.
UART0 and UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface. It also has the bus collision detection function that generates an interrupt
request if the TxD pin and the RxD pin are different in level.
Table 2.11.1 shows the comparison of functions of UART0 and UART2, and Figures 2.11.4 to 2.11.14
show the registers related to UARTi.
Table 2.11.1 Comparison of functions of UART0 and UART2
Function
UART0
UART2
CLK polarity selection
Possible (Note 1) Possible (Note 1)
LSB first / MSB first selection
Possible (Note 1) Possible (Note 2)
Continuous receive mode selection
Transfer clock output from multiple
pins selection
Serial data logic switch
Possible (Note 1) Possible (Note 1)
Impossible
Impossible
Impossible
Possible (Note 4)
Sleep mode selection
Possible (Note 3) Impossible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Impossible
CMOS output
Impossible
Possible
N-channel open-drain
output
Possible (Note 4)
Bus collision detection
Impossible
Possible
Notes 1: Only when clock synchronous serial I/O mode.
2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
3: Only when UART mode.
4: Using for SIM interface.
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Rev. 1.0