M306V5ME-XXXSP Datasheet, PDF (134/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(10) Address data communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit ad-
dressing format. The respective address communication formats is described below.
s 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I²Ci control register to “0.” The first
7-bit address data transmitted from the master is compared with the high-order 7-bit slave address
stored in the I²Ci address register. At the time of this comparison, address comparison of the RBW bit
of the I²Ci address register is not made. For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 2.11.45, (1) and (2).
s 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I²Ci control register to “1.” An
address comparison is made between the first-byte address data transmitted from the master and the
7-bit slave address stored in the I²Ci address register. At the time of this comparison, an address
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comparison between the RBW bit of the I²Ci address register and the R/W bit which is the last bit of
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the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit
which is the last bit of the address data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I²Ci status register is
set to “1.” After the second-byte address data is stored into the I²Ci data shift register, make an
address comparison between the second-byte data and the slave address by software. When the
address data of the 2nd bytes matches the slave address, set the RBW bit of the I²Ci address register
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to “1” by software. This processing can match the 7-bit slave address and R/W data, which are re-
ceived after a RESTART condition is detected, with the value of the I²Ci address register. For the data
transmission format when the 10-bit addressing format is selected, refer to Figure 2.11.45, (3) and (4).
Rev. 1.0
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