M306V5ME-XXXSP Datasheet, PDF (45/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.7.9 Rewrite Interrupt Control Register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR I
AND.B #00h, 0055h
NOP
NOP
FSET I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Rev. 1.0
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