M306V5ME-XXXSP Datasheet, PDF (38/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1,” a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set to
“1.” If an address other than the first address of the instruction in the address match interrupt register
is set, no address match interrupt occurs. For address match interrupt, see 2.11 Address match
Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INI instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts DMA generates.
• VSYNC interrupt
VSYNC interrupt occurs if a VSYNC edge is input.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 transmission, UART2 transmission interrupts
These are interrupts that the serial I/O transmission generates.
• UART0 reception, UART2 reception interrupts
These are interrupts that the serial I/O reception generates.
• Multi-master I²C-BUS interface 0 and multi-master I²C-BUS interface 1 interrupts
This is an interrupt that the serial I/O transmission/reception is completed, or a STOP condition is
detected.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
Rev. 1.0
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