M306V5ME-XXXSP Datasheet, PDF (102/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Transmit buffer ^{“1”}
empty flag (Tl)
“0”
CLKi
Data is set in UARTi transmit buffer register
TCLK ^{Transferred from UARTi transmit buffer register to UARTi transmit register}
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
Transmit
“1”
register empty
flag (TXEPT)
“0”
Transmit interrupt ^{“1”}
request bit (IR) “0”
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f 1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
Transmit buffer ^{“1”}
empty flag (Tl) “0”
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UARTi receive register
Receive complete ^{“1”}
to UARTi receive buffer register
flag (Rl)
“0”
Read out from UARTi receive buffer register
Receive interrupt ^{“1”}
request bit (IR) “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
fEXT: frequency of external clock
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Figure 2.11.17 Typical transmit/receive timings in clock synchronous serial I/O mode
102
Rev. 1.0