M306V5ME-XXXSP Datasheet, PDF (135/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and
in the ACK return mode is shown below.
Œ Set a slave address in the high-order 7 bits of the I²Ci address register and “0” in the RBW bit.
 Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I²Ci clock control register.
Ž Set “1016” in the I²Ci status register and hold the SCL at the HIGH.
 Set a communication enable status by setting “0816” in the I²Ci control register.
 Set the address data of the destination of transmission in the high-order 7 bits of the I²Ci data shift
register and set “0” in the least significant bit.
‘ Set “F016” in the I²Ci status register to generate a START condition. At this time, an SCL for 1 byte
and an ACK clock automatically occurs.
’ Set transmit data in the I²Ci data shift register. At this time, an SCL and an ACK clock automatically
occurs.
“ When transmitting control data of more than 1 byte, repeat step ’.
” Set “D016” in the I²Ci status register. After this, if ACK is not returned or transmission ends, a STOP
condition will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the
ACK non-return mode, using the addressing format, is shown below.
Œ Set a slave address in the high-order 7 bits of the I²Ci address register and “0” in the RBW bit.
 Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I²Ci clock control register.
Ž Set “1016” in the I²Ci status register and hold the SCL at the HIGH.
 Set a communication enable status by setting “0816” in the I²Ci control register.
 When a START condition is received, an address comparison is made.
‘
•When all transmitted address are“0” (general call):
AD0 of the I²Ci status register is set to “1”and an interrupt request signal occurs.
•When the transmitted addresses match the address set in Œ:
ASS of the I²Ci status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I²Ci status register are set to “0” and no interrupt request signal occurs.
’ Set dummy data in the I²Ci data shift register.
“ When receiving control data of more than 1 byte, repeat step ’.
” When a STOP condition is detected, the communication ends.
Rev. 1.0
135