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M306V5ME-XXXSP Datasheet, PDF (130/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
s Bit 4: I2C-BUS interface i interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the
PIN bit changes from â1â to â0.â At the same time, an interrupt request signal is sent to the CPU. The
PIN bit is set to â0â in synchronization with a falling edge of the last clock (including the ACK clock) of
an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the
PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt
request bit (IR) is set to â1â (interrupt requested) regardless of falling of PIN bit. When the PIN bit is â0,â
the SCL is kept in the â0â state and clock generation is disabled. Figure 2.11.41 shows an interrupt
request signal generating timing chart.
The PIN bit is set to â1â in any one of the following conditions.
⢠Writing â1â to the PIN bit
⢠Executing a write instruction to the I2Ci data shift register or the I2Ci transmit buffer register (See note).
⢠When the ESO bit is â0â
⢠At reset
Note : It takes 8 BCLK cycles or more until PIN bit becomes â1â after write instructions are executed
to these registers.
The conditions in which the PIN bit is set to â0â are shown below:
⢠Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
⢠Immediately after completion of 1-byte data reception
⢠In the slave reception mode, with ALS = â0â and immediately after completion of slave address or
general call address reception
⢠In the slave reception mode, with ALS = â1â and immediately after completion of address data reception
s Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to â0,â this bus system is not
busy and a START condition can be generated. When this bit is set to â1,â this bus system is busy and
the occurrence of a START condition is disabled by the START condition duplication prevention func-
tion (See note).
This flag can be written by software only in the master transmission mode. In the other modes, this bit is
set to â1â by detecting a START condition and set to â0â by detecting a STOP condition. When the ESO bit
of the I2Ci control register is â0â and at reset, the BB flag is kept in the â0â state.
s Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is â0,â the reception
mode is selected and the data of a transmitting device is received. When the bit is â1,â the transmission
mode is selected and address data and control data are output into the SDA in synchronization with
the clock generated on the SCL.
When the ALS bit of the I2Ci control register is â0â in the slave reception mode is selected, the TRX bit
___
is set to â1â (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master
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is â1.â When the ALS bit is â0â and the R/W bit is â0,â the TRX bit is cleared to â0â (receive).
The TRX bit is cleared to â0â in one of the following conditions.
⢠When arbitration lost is detected.
⢠When a STOP condition is detected.
⢠When occurence of a START condition is disabled by the START condition duplication prevention
function (Note).
⢠With MST = â0â and when a START condition is detected.
⢠With MST = â0â and when ACK non-return is detected.
⢠At reset
Rev. 1.0
130
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