M306V5ME-XXXSP Datasheet, PDF (132/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(7) START condition generation method
When the ESO bit of the I²Ci control register is “1,” execute a write instruction to the I²Ci status register
to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit
counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and
BB bit set timing are different in the standard clock mode and the high-speed clock mode. Refer to
Figure 2.11.42 for the START condition generation timing diagram, and Table 2.11.13 for the START
condition/STOP condition generation timing table.
I²Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Set time for
BB flag
Fig. 2.11.42 START condition generation timing diagram
(8) STOP condition generation method
When the ESO bit of the I²Ci control register is “1,” execute a write instruction to the I²Ci status register
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be
generated. The STOP condition generation timing and the BB flag reset timing are different in the
standard clock mode and the high-speed clock mode. Refer to Figure 2.11.43 for the STOP condition
generation timing diagram, and Table 2.11.13 for the START condition/STOP condition generation
timing table.
I²Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time
for
BB flag
Fig. 2.11.43 STOP condition generation timing diagram
Table 2.11.13 START condition/STOP condition generation timing table
Item
Setup time
Hold time
Set/reset time for BB flag
Standard Clock Mode
5.35 µs (53.5 cycles)
4.9 µs (49 cycles)
3.75 µs (37.5 cycles)
High-speed Clock Mode
1.85 µs (18.5 cycles)
2.4 µs (24 cycles)
0.85 µs (8.5 cycles)
Note: Absolute time at BCLK = 10 MHz. The value in parentheses denotes the number of BCLK cycles.
Rev. 1.0
132