M306V5ME-XXXSP Datasheet, PDF (114/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 2.11.9 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM
interface) (2)
Item
Error detection
Specification
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RxD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Notes 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
2: fEXT is input from the CLK2 pin.
3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Rev. 1.0
114