MT40A256M16GE-075E Datasheet, PDF (88/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 30: MPR Page and MPRx Definitions
Address MPR Location [7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note
MPR Page 0 – Read or Write (Data Patterns)
BA[1:0]
00 = MPR0
0
1
0
1
0
1
0
1
Read/
01 = MPR1
0
0
1
1
0
0
1
1
Write
(default
10 = MPR2
0
0
0
0
1
1
1
1
value lis-
11 = MPR3
0
0
0
0
0
0
0
0
ted)
MPR Page 1 – Read-only (Error Log)
BA[1:0]
00 = MPR0
A7
A6
A5
A4
A3
A2
A1
A0 Read-on-
01 = MPR1 CAS_n/A WE_n/A1 A13
A12
A11
A10
A9
A8
ly
15
4
10 = MPR2
PAR ACT_n BG1
BG0
BA1
BA0
A17 RAS_n/A
16
11 = MPR3 CRC er- CA pari- CA parity latency: [5] =
C2
ror sta- ty error MR5[2], [4] = MR5[1], [3] =
tus
status
MR5[0]
C1
C0
MPR Page 2 – Read-only (MRS Readout)
BA[1:0]
00 = MPR0
hPPR
support
sPPR
support
R_TT(WR)
MR2[11]
Temperature sen-
sor status²
CRC write
enable
MR2[12]
R_TT(WR) MR2[10:9]
Read-on-
ly
01 = MPR1
V_REFDQ
traing-
ing
range
MR6[6]
V_REFDQ training value: [6:1] = MR6[5:0]
Gear-
down
enable
MR3[3]
10 = MPR2
CAS latency: [7:3] = MR0[6:4,2,12]
CAS write latency [2:0] =
MR2[5:3]
11 = MPR3
R_TT(NOM): [7:5] = MR1[10:8]
R_TT(Park): [4:2] = MR5[8:6]
R_ON: [1:0] =
MR2[2:1]
MPR Page 3 – Read-only (Restricted, except for MPR3 [3:0])
BA[1:0]
00 = MPR0
DC
DC
DC
DC
DC
DC
DC
DC Read-on-
01 = MPR1
DC
DC
DC
DC
DC
DC
DC
DC
ly
10 = MPR2
DC
DC
DC
DC
DC
DC
DC
DC
11 = MPR3
DC
DC
DC
DC
MAC
MAC
MAC MAC
Notes: 1. DC = "Don't Care"
2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh;
MPR[4:3] 11 = Reserved
MPR Reads
MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not sup-
ported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ opera-
tion; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode.
READ commands for BC4 are supported with a starting column address of A[2:0] = 000
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
88
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