MT40A256M16GE-075E Datasheet, PDF (188/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Figure 120: ^tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
CK_c
CK_t
Command WRITE
Valid
Valid
Bank
Group
BGa
Bank Bank c
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
t_{WTR_L}
READ
BGa
Bank c
Valid
Address Col n
DQS, DQS_c
t_WPRE
t_WPST
Col n
DQ
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL
RL
Time Break
Transitioning Data
Don’t Care
Note: 1. ^tWTR_L: delay from start of internal write transaction to internal READ command to the
same bank group.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
188
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