MT40A256M16GE-075E Datasheet, PDF (244/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 194: Consecutive WRITE (BC4-Fixed) with 1^tCK Preamble and Write CRC in Same or Different
Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_WR
t_{CCD_S/L = 5}
2 Clocks
t_WTR
Bank Group
BGa
Address
BGa or
BGb
Address
Bank
Col n
DQS_t,
DQS_c
DQ x4,
BC = 4 (Fixed)
DQ x8/X16,
BC = 4 (Fixed)
WL = AL + CWL = 9
Bank
Col b
t_WPRE
DI
n
WL = AL + CWL = 9
DI DI DI
n+1 n+2 n+3
DI DI DI DI
n n+1 n+2 n+3
CRC CRC
DI DI DI DI
b b+1 b+2 b+3
CRC
DI DI DI DI
b b+1 b+2 b+3
t_WPST
CRC CRC
CRC
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1^tCK, ^tCDD_S/L = 5^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T16.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
244
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