MT40A256M16GE-075E Datasheet, PDF (2/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
-062E⁶
-068E⁵
-068⁵
-075E⁴
-075⁴
-083E³
-083³
-093E²
-093²
-107E¹
Data Rate (MT/s)
3200
2933
2933
2666
2666
2400
2400
2133
2133
1866
Target ^tRCD-^tRP-CL
22-22-22
20-20-20
21-21-21
18-18-18
19-19-19
16-16-16
17-17-17
15-15-15
16-16-16
13-13-13
t_{RCD (ns)}
13.75
13.64
14.32
13.5
14.25
13.32
14.16
14.06
15
13.92
t_{RP (ns)}
13.75
13.64
14.32
13.5
14.25
13.32
14.16
14.06
15
13.92
CL (ns)
13.75
13.64
14.32
13.5
14.25
13.32
14.16
14.06
15
13.92
Notes:
1. Backward compatible to 1600, CL = 11.
2. Backward compatible to 1600, CL = 11 and 1866, CL = 13.
3. Backward compatible to 1600, CL = 11; 1866, CL = 13; and 2133, CL = 15.
4. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.
5. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; 2400, CL = 17; and 2666, CL = 19. Speed
offering may have restricted availability.
6. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; 2400, CL = 17; 2666, CL = 19; and 2933,
CL = 20 and CL = 21. Speed offering may have restricted availability.
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page size¹
1024 Meg x 4
4
BG[1:0]
4
BA[1:0]
64K (A[15:0])
1K (A[9:0])
512B / 1KB²
512 Meg x 8
4
BG[1:0]
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
1KB
256 Meg x 16
2
BG0
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
2KB
Notes:
1. Page size is per bank, calculated as follows:
Page size = 2^COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
2. Die revision dependant.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
2
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