MT40A256M16GE-075E Datasheet, PDF (156/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Figure 91: Power-Down Entry After Read and Read with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
CK_c
CK_t
Command
RD or
RDA
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_IS t_CPDED
CKE
Tb0
Tb1
DES
Valid
Valid
Address Valid
DQS_t, DQS_c
DQ BL8
DQ BC4
RL = AL + CL
Valid
t_PD
DI DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
DI DI DI DI
n n+1 n+2 n+3
t_RDPDEN
Power-Down
entry
Transitioning Data
Time Break
Don’t Care
Note: 1. DI n (or b) = data-in from column n (or b).
Figure 92: Power-Down Entry After Write and Write with Auto Precharge
T0
CK_c
CK_t
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CKE
Address
Bank,
Col n
A10
DQS_t, DQS_c
DQ BL8
DQ BC4
WL = AL + CWL
WR
DI
DI
DI
DI
DI
DI
DI
DI
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
Start internal
precharge
DI
DI
DI
DI
n
n+1 n+2 n+3
t_WRAPDEN
Tb1
Tb2
Tc0
DES
DES
DES
t_IS
t_CPDED
t_PD
Power-Down
entry
Transitioning Data 7LPH%UHDN
Tc1
Valid
Valid
Valid
'RQ¶W&DUH
Notes: 1. DI n (or b) = data-in from column n (or b).
2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-
tion of the PRECHARGE command.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
156
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