MT40A256M16GE-075E Datasheet, PDF (302/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Definitions for ^tADC, ^tAONAS, and ^tAOFAS are provided in the Table 130 (page 302) and
shown in Figure 238 (page 303) and Figure 240 (page 304). Measurement reference set-
tings are provided in the subsequent Table 131 (page 302).
The ^tADC for the dynamic ODT case and read disable ODT cases are represented by
t_{ADC of Direct ODT Control case.}
Table 130: ODT Timing Definitions
Parameter
Begin Point Definition
t_ADC
Rising edge of CK_t, CK_c defined by the end point of
DODTLoff
Rising edge of CK_t, CK_c defined by the end point of
DODTLon
Rising edge of CK_t, CK_c defined by the end point of
ODTLcnw
Rising edge of CK_t, CK_c defined by the end point of
ODTLcwn4 or ODTLcwn8
t_AONAS
Rising edge of CK_t, CK_c with ODT being first registered
HIGH
t_AOFAS
Rising edge of CK_t, CK_c with ODT being first registered
LOW
End Point Definition
Extrapolated point at V_RTT,nom
Extrapolated point at V_SSQ
Extrapolated point at V_RTT,nom
Extrapolated point at V_SSQ
Extrapolated point at V_SSQ
Extrapolated point at V_RTT,nom
Figure
Figure 238
(page 303)
Figure 238
(page 303)
Figure 239
(page 303)
Figure 239
(page 303)
Figure 240
(page 304)
Figure 240
(page 304)
Table 131: Reference Settings for ODT Timing Measurements
Measure
Parameter
t_ADC
t_AONAS
t_AOFAS
R_TT(Park)
Disable
–
Disable
Disable
R_TT(NOM)
R_ZQΩ
R_ZQΩ
R_ZQΩ
R_ZQΩ
R_TT(WR)
–
High-Z
–
–
VSW1
0.20V
0.20V
0.20V
0.20V
VSW2
0.40V
0.40V
0.40V
0.40V
Note
1, 2, 4
1, 3, 5
1, 2, 6
1, 2, 6
Notes:
1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for R_TT(NOM) setting; MR5 has
A8 = 0, A7 = 0, A6 = 0 for R_TT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for
R_TT(WR) setting.
2. ODT state change is controlled by ODT pin.
3. ODT state change is controlled by a WRITE command.
4. Refer to Figure 238 (page 303).
5. Refer to Figure 239 (page 303).
6. Refer to Figure 240 (page 304).
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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