MT40A256M16GE-075E Datasheet, PDF (83/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

Figure 29: Consecutive READ BL8, CAL3, 1^tCK Preamble, Different Bank Group
CK_c
CK_t
CS_n
Command
Bank Group
Address
Address
DQS_t, DQS_c
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
t_{CAL = 3}
DES
DES
READ
BG a
Bank,
Col n
t_{CAL = 3}
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
BG b
Bank,
Col b
t_{RPRE (1nCK)}
t_RPST
RL = 11
RL = 11
D_OUT
n
D_OUT
n+1
D_OUT
n+2
D_OUT
n+3
D_OUT
n+4
D_OUT
n+5
D_OUT
n+6
D_OUT
n+7
D_OUT
b
D_OUT
b+7
D_OUT
b+2
D_OUT
b+3
D_OUT
b+4
D_OUT
b+5
D_OUT
b+6
D_OUT
b+7
Transitioning Data
Don’t Care
Notes:
1. BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1^tCK.
2. D_OUT n = data-out from column n; D_OUT b = data-out from column b.
3. DES commands are shown for ease of illustration, other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and
T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.
6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.
Figure 30: Consecutive READ BL8, CAL4, 1^tCK Preamble, Different Bank Group
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Notes:
1. BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1^tCK.
2. D_OUT n = data-out from column n; D_OUT b = data-out from column b.
3. DES commands are shown for ease of illustration, other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and
T8.