MT40A256M16GE-075E Datasheet, PDF (349/365 Pages) Micron Technology – Temperature controlled refresh (TCR)

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
Direct ODT turn-on latency
Direct ODT turn-off latency
R_TT dynamic change skew
Asynchronous R_TT(NOM) turn-on delay
(DLL off)
Asynchronous R_TT(NOM) turn-off delay
(DLL off)
ODT HIGH time with WRITE command
and BL8
ODT HIGH time without WRITE command
or with WRITE command and BC4
First DQS_t, DQS_c rising edge after write
leveling mode is programmed
DQS_t, DQS_c delay after write leveling
mode is programmed
Write leveling setup from rising CK_t,
CK_c crossing to rising DQS_t, DQS_c
crossing
Write leveling hold from rising DQS_t,
DQS_c crossing to rising CK_t, CK_c cross-
ing
Write leveling output delay
Write leveling output error
Exit reset from CKE HIGH to a valid MRS
gear-down
CKE HIGH assert to gear-down enable
time)
MRS command to sync pulse time
Sync pulse to first valid command
Gear-down setup time
Gear-down hold time
Symbol
DODTLon
DODTLoff
t_ADC
t_AONAS
DDR4-1600
Min Max
0.3
0.7
1
9
DDR4-1866
DDR4-2133
Min Max Min Max
WL - 2 = CWL + AL + PL - 2
WL - 2 = CWL + AL + PL - 2
0.3
0.7
0.3
0.7
1
9
1
9
t_AOFAS
1
9
1
9
1
9
ODTH8 1^tCK
6
–
6
–
6
–
ODTH8 2^tCK
7
–
7
–
7
–
ODTH4 1^tCK
4
–
4
–
4
–
ODTH4 2^tCK
5
–
5
–
5
–
Write Leveling Timing
t_WLMRD
40
–
40
–
40
–
t_WLDQSEN
25
–
25
–
25
–
t_WLS
0.13
–
0.13
–
0.13
–
t_WLH
0.13
–
0.13
–
0.13
–
t_WLO
0
9.5
0
9.5
0
9.5
t_WLOE
0
2
0
2
0
2
Gear-Down Timing (Not Supported Below DDR4-2666)
t_{XPR_GEAR}
N/A
N/A
N/A
t_{XS_GEAR}
N/A
N/A
N/A
t_{SYNC_GEAR}
t_{CMD_GEAR}
t_{GEAR_setup}
t_{GEAR_hold}
N/A
N/A
N/A
–
N/A
–
N/A
N/A
N/A
–
N/A
–
N/A
N/A
N/A
–
N/A
–
DDR4-2400
Min Max
0.3
0.7
1
9
Unit
CK
CK
CK
ns
Notes
1
9
ns
6
–
CK
7
–
4
–
CK
5
–
40
25
0.13
0.13
0
0
–
CK
–
CK
–
t_CK
(AVG)
–
t_CK
(AVG)
9.5
ns
2
ns
N/A
CK
N/A
CK
N/A
CK
N/A
CK
N/A
–
CK
N/A
–
CK