N25Q128A13ESE40G Datasheet, PDF (61/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

128Mb, 3V, Multiple I/O Serial Flash Memory
Power-Up and Power-Down
Table 30: Power-Up Timing and V_WI Threshold
Note 1 applies to entire table
Symbol
t_VTR
t_VTW
V_WI
Parameter
V_CC,min to read
V_CC,min to device fully accessible
Write inhibit voltage
Note: 1. Parameters listed are characterized only.
Min
–
–
1.5
Max
150
150
2.5
Unit
µs
µs
V
Power Loss Rescue Sequence
If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER
command, after the next power-on, the device might begin in an undetermined state
(XIP mode or an unnecessary protocol). If this happens, until the next power-up, a res-
cue sequence must reset the device to a fixed state (extended SPI protocol without XIP).
After the rescue sequence, the issue should be resolved by running the WRITE NONVO-
LATILE CONFIGURATION REGISTER command again. The rescue sequence is com-
posed of two parts that must be run in the correct order. During the entire sequence,
t_{SHSL2 must be at least 50ns. The first part of the sequence is DQ0 (PAD DATA) and}
DQ3 (PAD HOLD) equal to 1 for the situations listed below:
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
The second part of the sequence is exiting from dual or quad SPI protocol by using the
following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S#
becomes HIGH before 9th clock cycle.
After this two-part sequence the extended SPI protocol is active.
PDF: 09005aef845665fe
n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
61
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.