N25Q128A13ESE40G Datasheet, PDF(21/81 Page) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

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N25Q128A13ESE40G Datasheet, PDF (21/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

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128Mb, 3V, Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Nonvolatile and Volatile Configuration Registers

Table 10: Nonvolatile Configuration Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

Description

Notes

15:12 Number of

dummy clock

cycles

0000 (identical to 1111)

0001

0010

1101

1110

1111

Sets the number of dummy clock cycles subse-

2, 3

quent to all FAST READ commands.

The default setting targets the maximum al-

lowed frequency and guarantees backward com-

patibility.

11:9 XIP mode at 000 = XIP: Fast Read

power-on re- 001 = XIP: Dual Output Fast Read

set

010 = XIP: Dual I/O Fast Read

011 = XIP: Quad Output Fast Read

100 = XIP: Quad I/O Fast Read

101 = Reserved

110 = Reserved

111 = Disabled (Default)

Enables the device to operate in the selected XIP

mode immediately after power-on reset.

8:6 Output driver 000 = Reserved

strength

001 = 90 Ohms

010 = 60 Ohms

011 = 45 Ohms

100 = Reserved

101 = 20 Ohms

110 = 15 Ohms

111 = 30 (Default)

Optimizes impedance at VCC/2 output voltage.

5 Reserved

"Don't Care."

4 Reset/hold

0 = Disabled

1 = Enabled (Default)

Enables or disables hold or reset.

(Available on dedicated part numbers.)

3 Quad I/O pro- 0 = Enabled

Enables or disables quad I/O protocol.

tocol

1 = Disabled (Default, Extended SPI prot-

cocol)

2 Dual I/O pro- 0 = Enabled

Enables or disables dual I/O protocol.

tocol

1 = Disabled (Default, Extended SPI pro-

tocol)

1:0 Reserved

"Don't Care."

Notes:

1. Settings determine device memory configuration after power-on. The device ships from

the factory with all bits erased to 1 (FFFFh). The register is read from or written to by

READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURA-

TION REGISTER commands, respectively.

2. The 0000 and 1111 settings are identical in that they both define the default state,

which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility.

3. If the number of dummy clock cycles is insufficient for the operating frequency, the

memory reads wrong data. The number of cycles must be set according to and sufficient

PDF: 09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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