N25Q128A13ESE40G Datasheet, PDF (31/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

128Mb, 3V, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input
on DQ[3:0], followed by the data bytes.
If S# is not driven HIGH, the command is not executed, the flag status register error bits
are not set and the write enable latch remains set to 1. Reserved bits are not affected by
this command.
READ LOCK REGISTER Command
To execute the READ LOCK REGISTER command, S# is driven LOW. For extended SPI
protocol, the command code is input on DQ0, followed by three address bytes that
point to a location in the sector. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. Each address
bit is latched in during the rising edge of the clock. For extended SPI protocol, data is
shifted out on DQ1 at a maximum frequency ^fC during the falling edge of the clock. For
dual SPI protocol, data is shifted out on DQ[1:0], and for quad SPI protocol, data is shif-
ted out on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during
data output.
When the register is read continuously, the same byte is output repeatedly. Any READ
LOCK REGISTER command that is executed while an ERASE, PROGRAM, or WRITE cy-
cle is in progress is rejected with no affect on the cycle in progress.
Table 17: Lock Register
Note 1 applies to entire table
Bit Name
7:2 Reserved
1
Sector lock down
0
Sector write lock
Settings
Description
0
Bit values are 0.
0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,
1 = Set
which means sector lock down and sector write lock bits can be
set.
When this bit set, neither of the lock register bits can be written
to until the next power cycle.
0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,
1 = Set
which means that PROGRAM and ERASE operations in this sector
can be executed and sector content modified.
When this bit is set, PROGRAM and ERASE operations in this sec-
tor will not be executed.
Note: 1. Sector lock register bits 1:0 are written to by the WRITE LOCK REGISTER command. The
command will not execute unless the sector lock down bit is cleared.
PDF: 09005aef845665fe
n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
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