N25Q128A13ESE40G Datasheet, PDF (23/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

128Mb, 3V, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 12: Sequence of Bytes During Wrap
Starting Address
0
1
15
31
63
16-Byte Wrap
0-1-2- . . . -15-0-1- . .
1-2- . . . -15-0-1-2- . .
15-0-1-2-3- . . . -15-0-1- . .
31-16-17- . . . -31-16-17- . .
63-48-49- . . . -63-48-49- . .
32-Byte Wrap
0-1-2- . . . -31-0-1- . .
1-2- . . . -31-0-1-2- . .
15-16-17- . . . -31-0-1- . .
31-0-1-2-3- . . . -31-0-1- . .
63-32-33- . . . -63-32-33- . .
64-Byte Wrap
0-1-2- . . . -63-0-1- . .
1-2- . . . -63-0-1-2- . .
15-16-17- . . . -63-0-1- . .
31-32-33- . . . -63-0-1- . .
63-0-1- . . . -63-0-1- . .
Table 13: Supported Clock Frequencies
Note 1 applies to entire table
Number of
Dummy
Clock Cycles
FAST READ
1
90
2
100
3
108
4
108
5
108
6
108
7
108
8
108
9
108
10
108
DUAL OUTPUT
FAST READ
80
90
100
105
108
108
108
108
108
108
DUAL I/O FAST
READ
50
70
80
90
100
105
108
108
108
108
QUAD OUTPUT
FAST READ
43
60
75
90
100
105
108
108
108
108
QUAD I/O FAST
READ
30
40
50
60
70
80
86
95
105
108
Unit
MHz
Note: 1. Values are guaranteed by characterization and not 100% tested in production.
Enhanced Volatile Configuration Register
Table 14: Enhanced Volatile Configuration Register Bit Definitions
Note 1 applies to entire table
Bit Name
7
Quad I/O protocol
6
Dual I/O protocol
5
Reserved
4
Reset/hold
Settings
Description
0 = Enabled
Enables or disables quad I/O protocol.
1 = Disabled (Default,
extended SPI protocol)
0 = Enabled
Enables or disables dual I/O protocol.
1 = Disabled (Default,
extended SPI protocol)
X = Default
0b = Fixed value.
0 = Disabled
Enables or disables hold or reset.
1 = Enabled (Default) (Available on dedicated part numbers.)
Notes
2
2
PDF: 09005aef845665fe
n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
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