N25Q128A13ESE40G Datasheet, PDF (30/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

Figure 11: WRITE REGISTER Command
128Mb, 3V, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
Extended
C
0
7
8
9
10
11
12
13
14
15
LSB
DQ0
Command
D_IN
D_IN
D_IN
D_IN
MSB
MSB
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
Dual
0
C
DQ[1:0]
Command
MSB
3
4
LSB
D_IN
MSB
5
6
D_IN
D_IN
7
LSB
D_IN
D_IN
Quad
C
0
1
2
3
DQ[3:0]
Command
MSB
LSB
D_IN
MSB
LSB
D_IN
D_IN
Notes:
1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER.
2. Waveform must be extended for each protocol, to 23 for extended, 11 for dual, and 5
for quad.
3. A WRITE NONVOLATILE CONFIGURATION REGISTER operation requires data being sent
starting from least significant byte.
WRITE NONVOLATILE CONFIGURATION REGISTER Command
To execute the WRITE NONVOLATILE CONFIGURATION REGISTER command, the
WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is
driven LOW and held LOW until the 16th bit of the last data byte has been latched in,
after which it must be driven HIGH. For extended SPI protocol, the command code is
input on DQ0, followed by two data bytes. For dual SPI protocol, the command code is
input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code
is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation,
which is self-timed, is initiated; its duration is ^tWNVCR.
When the operation is in progress, the write in progress bit is set to 1. The write enable
latch bit is cleared to 0, whether the operation is successful or not. The status register
and flag status register can be polled for the operation status. When the operation com-
pletes, the write in progress bit is cleared to 0, whether the operation is successful or
not. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1.
WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command
To execute a WRITE VOLATILE CONFIGURATION REGISTER command or a WRITE
ENHANCED VOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE
command must be executed to set the write enable latch bit to 1. S# is driven LOW and
held LOW until the eighth bit of the last data byte has been latched in, after which it
must be driven HIGH. For extended SPI protocol, the command code is input on DQ0,
followed by the data bytes. For dual SPI protocol, the command code is input on
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n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
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