N25Q128A13ESE40G Datasheet, PDF (5/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

128Mb, 3V, Multiple I/O Serial Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ........................................................................................................................... 10
Table 2: Sectors[255:0] ................................................................................................................................... 13
Table 3: Data Protection using Device Protocols ............................................................................................. 14
Table 4: Memory Sector Protection Truth Table .............................................................................................. 14
Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14
Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 15
Table 7: SPI Modes ........................................................................................................................................ 16
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 18
Table 9: Status Register Bit Definitions ........................................................................................................... 20
Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 21
Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 22
Table 12: Sequence of Bytes During Wrap ....................................................................................................... 23
Table 13: Supported Clock Frequencies .......................................................................................................... 23
Table 14: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 23
Table 15: Flag Status Register Bit Definitions .................................................................................................. 24
Table 16: Command Set ................................................................................................................................. 26
Table 17: Lock Register .................................................................................................................................. 31
Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 34
Table 19: Read ID Data Out ............................................................................................................................ 34
Table 20: Extended Device ID, First Byte ......................................................................................................... 34
Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................ 36
Table 22: Parameter ID .................................................................................................................................. 36
Table 23: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 38
Table 24: Data/Address Lines for PROGRAM Commands ................................................................................ 42
Table 25: Suspend Parameters ....................................................................................................................... 52
Table 26: Operations Allowed/Disallowed During Device States ...................................................................... 53
Table 27: OTP Control Byte (Byte 64) .............................................................................................................. 55
Table 28: XIP Confirmation Bit ....................................................................................................................... 58
Table 29: Effects of Running XIP in Different Protocols .................................................................................... 58
Table 30: Power-Up Timing and V_WI Threshold ............................................................................................... 61
Table 31: AC RESET Conditions ...................................................................................................................... 62
Table 32: Absolute Ratings ............................................................................................................................. 67
Table 33: Operating Conditions ...................................................................................................................... 67
Table 34: Input/Output Capacitance .............................................................................................................. 67
Table 35: AC Timing Input/Output Conditions ............................................................................................... 68
Table 36: DC Current Characteristics and Operating Conditions ...................................................................... 69
Table 37: DC Voltage Characteristics and Operating Conditions ...................................................................... 69
Table 38: AC Characteristics and Operating Conditions ................................................................................... 70
Table 39: Part Number Information ................................................................................................................ 78
Table 40: Package Details ............................................................................................................................... 79
PDF: 09005aef845665fe
n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
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