N25Q128A13ESE40G Datasheet, PDF (60/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A

128Mb, 3V, Multiple I/O Serial Flash Memory
Power-Up and Power-Down
Power-Up and Power-Down
Power-Up and Power-Down Requirements
At power-up and power-down, the device must not be selected; that is, S# must follow
the voltage applied on V_CC until V_CC reaches the correct values: V_CC,min at power-up and
V_SS at power-down.
To avoid data corruption and inadvertent WRITE operations during power-up, a power-
on reset circuit is included. The logic inside the device is held to RESET while V_CC is less
than the power-on reset threshold voltage shown here; all operations are disabled, and
the device does not respond to any instruction. During a standard power-up phase, the
device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS
REGISTER. These operations can be used to check the memory internal state. After
power-up, the device is in standby power mode; the write enable latch bit is reset; the
write in progress bit is reset; and the lock registers are configured as: (write lock bit, lock
down bit) = (0,0).
Normal precautions must be taken for supply line decoupling to stabilize the V_CC sup-
ply. Each device in a system should have the V_CC line decoupled by a suitable capacitor
(typically 100nF) close to the package pins. At power-down, when V_CC drops from the
operating voltage to below the power-on-reset threshold voltage shown here, all opera-
tions are disabled and the device does not respond to any command.
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,
data corruption may result.
V_PPH must be applied only when V_CC is stable and in the V_CC,min to V_CC,max voltage
range.
Figure 32: Power-Up Timing
V_CC
V_CC,max
Chip selection not allowed
V_CC,min
V_WI
Chip
reset
t_{VTW =} t_VTR
Polling allowed
SPI protocol
WIP = 1
WEL = 0
Device fully accessible
Starting protocol
defined by NVCR
WIP = 0
WEL = 0
Time
PDF: 09005aef845665fe
n25q_128mb_3v_65nm.pdf - Rev. P 06/13 EN
60
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