PIC18LF4610T-I Datasheet, PDF (99/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
TABLE 9-3: PORTB I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/FLT0/
RB0
AN12
0
O
DIG LATB<0> data output; not affected by analog input.
1
I
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
INT0
1
I
ST External interrupt 0 input.
FLT0
1
I
ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
AN12
1
I
ANA A/D input channel 12.⁽¹⁾
RB1/INT1/AN10
RB1
0
O
DIG LATB<1> data output; not affected by analog input.
1
I
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
INT1
1
I
ST External interrupt 1 input.
AN10
1
I
ANA A/D input channel 10.⁽¹⁾
RB2/INT2/AN8
RB2
0
O
DIG LATB<2> data output; not affected by analog input.
1
I
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
INT2
AN8
1
I
ST External interrupt 2 input.
1
I
ANA A/D input channel 8.⁽¹⁾
RB3/AN9/CCP2
RB3
0
O
DIG LATB<3> data output; not affected by analog input.
1
AN9
1
CCP2⁽²⁾
0
I
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
I
ANA A/D input channel 9.⁽¹⁾
O
DIG CCP2 compare and PWM output.
1
I
ST CCP2 capture input
RB4/KBI0/AN11
RB4
0
O
DIG LATB<4> data output; not affected by analog input.
1
I
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
KBI0
1
I
TTL Interrupt on pin change.
AN11
1
I
ANA A/D input channel 11.⁽¹⁾
RB5/KBI1/PGM
RB5
0
O
DIG LATB<5> data output.
1
I
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1
1
I
TTL Interrupt on pin change.
PGM
x
I
ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
RB6/KBI2/PGC
RB6
0
O
DIG LATB<6> data output.
1
I
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2
PGC
1
I
TTL Interrupt on pin change.
x
I
ST Serial execution (ICSP) clock input for ICSP and ICD operation.⁽³⁾
RB7/KBI3/PGD
RB7
0
O
DIG LATB<7> data output.
1
I
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3
PGD
1
I
TTL Interrupt on pin change.
x
O
DIG Serial execution data output for ICSP and ICD operation.⁽³⁾
x
I
ST Serial execution data input for ICSP and ICD operation.⁽³⁾
Legend:
Note 1:
2:
3:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
© 2009 Microchip Technology Inc.
DS39636D-page 101