PIC18LF4610T-I Datasheet, PDF (203/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
FIGURE 17-7:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
PIR1
PIE1
IPR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
51
PSPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
54
PSPIE⁽¹⁾ ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
PSPIP⁽¹⁾ ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
53
RCREG
EUSART Receive Register
53
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
53
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
53
SPBRGH EUSART Baud Rate Generator Register, High Byte
53
SPBRG
EUSART Baud Rate Generator Register, Low Byte
53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.
© 2009 Microchip Technology Inc.
DS39636D-page 205