PIC18LF4610T-I Datasheet, PDF (150/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
TABLE 15-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
RCON
PIR1
PIE1
IPR1
GIE/GIEH PEIE/GIEL
IPEN SBOREN⁽²⁾
PSPIF⁽¹⁾
ADIF
PSPIE⁽¹⁾
ADIE
PSPIP⁽¹⁾
ADIP
TMR0IE
—
RCIF
RCIE
RCIP
INT0IE
RI
TXIF
TXIE
TXIP
RBIE
TMR0IF INT0IF
RBIF
51
TO
PD
POR
BOR
50
SSPIF CCP1IF TMR2IF TMR1IF
54
SSPIE CCP1IE TMR2IE TMR1IE
54
SSPIP CCP1IP TMR2IP TMR1IP
54
PIR2
OSCFIF
CMIF
—
—
BCLIF HLVDIF TMR3IF CCP2IF
54
PIE2
OSCFIE CMIE
—
—
BCLIE HLVDIE TMR3IE CCP2IE
54
IPR2
OSCFIP CMIP
—
—
BCLIP HLVDIP TMR3IP CCP2IP
54
TRISB
PORTB Data Direction Control Register
54
TRISC
PORTC Data Direction Control Register
54
TRISD
PORTD Data Direction Control Register
54
TMR1L
Timer1 Register Low Byte
52
TMR1H Timer1 Register High Byte
52
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
TMR2
Timer2 Register
52
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
PR2
Timer2 Period Register
52
TMR3L
Timer3 Register Low Byte
53
TMR3H Timer3 Register High Byte
53
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 Low Byte
53
CCPR1H Capture/Compare/PWM Register 1 High Byte
53
CCP1CON P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1⁽¹⁾ PSSBD0⁽¹⁾ 53
PWM1CON PRSEN PDC6⁽¹⁾
PDC5⁽¹⁾
PDC4⁽¹⁾
PDC3⁽¹⁾ PDC2⁽¹⁾ PDC1⁽¹⁾ PDC0⁽¹⁾
53
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
These bits are unimplemented on 28-pin devices and read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled
and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
DS39636D-page 152
© 2009 Microchip Technology Inc.