PIC18LF4610T-I Datasheet, PDF (251/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
22.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 16- and 32-Kbyte devices and the specific code
protection bit associated with each block.
Figure 22-6 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
FIGURE 22-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2410/2510/4410/4510
MEMORY SIZE/DEVICE
16 Kbytes
32 Kbytes
Address
(PIC18F2410/4410) (PIC18F2510/4510) Range
Block Code Protection
Controlled By:
Boot Block
Block 0
Boot Block
Block 0
000000h
0007FFh
000800h
001FFFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
Block 1
Block 1
Block 2
002000h
003FFFh
004000h
005FFFh
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
Block 3
006000h
007FFFh
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
© 2009 Microchip Technology Inc.
DS39636D-page 253