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PIC18LF4610T-I Datasheet, PDF (129/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers
PIC18F2X1X/4X1X
14.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2X1X/4X1X devices all have two CCP
(Capture/Compare/PWM) modules. Each module con-
tains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules
(CCP1 and CCP2) operate as described in this chapter.
In 40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module with standard Capture and
Compare modes and Enhanced PWM modes. The
ECCP implementation is discussed in Section 15.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”.
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
Note: Throughout this section and Section 15.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to gener-
ically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of whether
the CCP module is a standard or Enhanced
implementation.
REGISTER 14-1:
CCPXCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
—
—
DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCPxIF bit is set)
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc.
DS39636D-page 131