PIC18LF4610T-I Datasheet, PDF (246/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
22.2 Watchdog Timer (WDT)
For PIC18F2X1X/4X1X devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
22.2.1 CONTROL REGISTER
Register 22-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT Configura-
tion bit, but only if the Configuration bit has disabled the
WDT.
FIGURE 22-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
INTRC Source
Change on IRCF bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
WDT Counter
÷128
Programmable Postscaler ^Reset
1:1 to 1:32,768
4
Wake-up From
Power-Managed
Modes
WDT
Reset
DS39636D-page 248
© 2009 Microchip Technology Inc.