PIC18LF4610T-I Datasheet, PDF (76/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
6.2 Control Registers
Two control registers are used in conjunction with the
TBLRD instruction: the TABLAT register and the
TBLPTR register set.
6.2.1 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.2
TBLPTR – TABLE POINTER
REGISTER
The Table Pointer register (TBLPTR) addresses a byte
within the program memory. It is comprised of three
SFR registers: Table Pointer Upper Byte, Table Pointer
High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six
bits of TBLPTRU are used with TBLPTRH and
TBLPTRL, to form a 22-bit wide pointer.
The contents of TBLPTR indicate a location in program
memory space. The low-order 21 bits allow the device
to address the full 2 Mbytes of program memory space.
The 22nd bit allows access to the configuration space,
including the Device ID, user ID locations and the
Configuration bits.
The TBLPTR register set is updated when executing a
TBLRD in one of four ways, based on the instruction’s
arguments. These are detailed in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TABLE 6-1:
TABLE POINTER
OPERATIONS WITH TBLRD
INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLPTR is not modified
TBLPTR is incremented after the read
TBLPTR is decremented after the read
TBLPTR is incremented before the read
6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-2
shows the interface between the internal program
memory and the TABLAT.
A typical method for reading data from program memory
is shown in Example 6-1.
FIGURE 6-2:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address) (Odd Byte Address)
Instruction Register
(IR)
FETCH
DS39636D-page 78
TBLPTR = xxxxx1
TBLPTR = xxxxx0
TBLRD
TABLAT
Read Register
© 2009 Microchip Technology Inc.