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PIC18LF4610T-I Datasheet, PDF (269/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers | |||
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PIC18F2X1X/4X1X
BRA
Unconditional Branch
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
BRA n
-1024 ⤠n ⤠1023
(PC) + 2 + 2n â PC
None
1101 0nnn nnnn nnnn
Add the 2âs complement number â2nâ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1
2
Q2
Read literal
ânâ
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
PC
=
BRA Jump
address (HERE)
address (Jump)
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Set f
BSF f, b {,a}
0 ⤠f ⤠255
0â¤bâ¤7
a â [0,1]
1 â f<b>
None
1000 bbba ffff ffff
Bit âbâ in register âfâ is set.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ⤠95 (5Fh). See
Section 23.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
BSF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 1
0Ah
8Ah
© 2009 Microchip Technology Inc.
DS39636D-page 271
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