PIC18LF4610T-I Datasheet, PDF (134/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
14.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Note:
Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending
on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
Figure 14-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 14.4.4
“Setup for PWM Operation”.
FIGURE 14-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
CCPxCON<5:4>
CCPRxL
CCPRxH (Slave)
Comparator
RQ
CCPx Output
TMR2
(Note 1)
S
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Corresponding
TRIS bit
Note 1: The 8-bit TMR2 value is concatenated with 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
A PWM output (Figure 14-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 14-4:
PWM OUTPUT
Period
14.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 14-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
Note:
The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
14.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 14-2:
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPRxL and CCPxCON<5:4> can be written to at any
time but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
Duty Cycle
TMR2 = PR2
TMR2 = PR2
TMR2 = Duty Cycle
DS39636D-page 136
© 2009 Microchip Technology Inc.