PIC18LF4610T-I Datasheet, PDF (65/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers

PIC18F2X1X/4X1X
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 51, 56
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 51, 56
TOSL
STKPTR
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL⁽⁶⁾ STKUNF⁽⁶⁾
—
0000 0000 51, 56
SP4
SP3
SP2
SP1
SP0 00-0 0000 51, 57
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000 51, 56
PCLATH
Holding Register for PC<15:8>
0000 0000 51, 56
PCL
PC Low Byte (PC<7:0>)
0000 0000 51, 56
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 51, 79
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 51, 79
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 51, 79
TABLAT
Program Memory Table Latch
0000 0000 51, 79
PRODH
Product Register High Byte
xxxx xxxx 51, 81
PRODL
Product Register Low Byte
xxxx xxxx 51, 81
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 51, 85
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 51, 86
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 51, 87
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
51, 72
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
51, 72
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
51, 72
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
51, 72
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
51, 72
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000 51, 72
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 51, 72
WREG
Working Register
xxxx xxxx 51
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
51, 72
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
51, 72
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
51, 72
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
51, 72
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
51, 72
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 52, 72
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 52, 72
BSR
—
—
—
—
Bank Select Register
---- 0000 52, 61
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
52, 72
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
52, 72
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
52, 72
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
52, 72
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
52, 72
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 52, 72
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 52, 72
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 52, 70
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
© 2009 Microchip Technology Inc.
DS39636D-page 67