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PIC18LF4610T-I Datasheet, PDF (341/376 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers | |||
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PIC18F2X1X/4X1X
FIGURE 25-16:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 25-5 for load conditions.
TABLE 25-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TssL2scH, SS â to SCK â or SCK â Input
TssL2scL
TCY
â
71 TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 â
40
â
72 TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 â
40
â
73A Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 â
74 TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
â
75 TdoR
SDO Data Output Rise Time
PIC18FXXXX
â
25
PIC18LFXXXX
45
76 TdoF
SDO Data Output Fall Time
â
25
77 TssH2doZ SSâ to SDO Output High-Impedance
10
50
78 TscR
SCK Output Rise Time
(Master mode)
PIC18FXXXX
PIC18LFXXXX
â
25
â
45
79 TscF
SCK Output Fall Time (Master mode)
â
25
80 TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX
TscL2doV Edge
PIC18LFXXXX
â
50
â
100
82 TssL2doV SDO Data Output Valid after SS â PIC18FXXXX
Edge
PIC18LFXXXX
â
50
â
100
83 TscH2ssH, SS â after SCK Edge
TscL2ssH
1.5 TCY + 40 â
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns VDD = 2.0V
ns
© 2009 Microchip Technology Inc.
DS39636D-page 343
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