PIC24HJ12GP201 Datasheet, PDF (98/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
9.5 Peripheral Pin Select Registers
The PIC24HJ12GP201/202 devices implement 17
registers for remappable peripheral configuration:
• Input Remappable Peripheral Registers (9)
• Output Remappable Peripheral Registers (8)
Note:
Input and Output Register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 9.4.4.1 “Control Register
Lock” for a specific command sequence.
REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
bit 15
U-0
U-0
R/W-1
R/W-1
R/W-1
—
—
INT1R<4:0>
R/W-1
R/W-1
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-0
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin bits
11111 = Input tied to VSS
01111 = Input tied to RP15
•
•
•
00001 = Input tied to RP1
00000 = Input tied to RP0
Unimplemented: Read as ‘0’
DS70282B-page 96
Preliminary
© 2007 Microchip Technology Inc.