PIC24HJ12GP201 Datasheet, PDF (45/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
5.0 RESETS
Note:
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
chapters.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode, Uninitialized W
Register Reset, and Security Reset
• CM: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
Any active source of Reset makes the SYSRST signal
active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user
application can set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software
does not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
MCLR
VDD
Glitch Filter
WDT
Module
Sleep or Idle
VDD Rise
Detect
Internal
Regulator
POR
BOR
SYSRST
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 43