PIC24HJ12GP201 Datasheet, PDF (127/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
14.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note:
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
chapters.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, analog-to-digital (A/D)
converters, etc. The SPI module is compatible with
SPI and SIOP from Motorola^®.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of 4 pins:
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active low slave select).
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
14.1 Interrupts
A series of 8 or 16 clock pulses shift out bits from the
SPIxSR to SDOx pin and simultaneously shift in data
from the SDIx pin. An interrupt is generated when the
transfer is complete and the corresponding interrupt flag
bit (SPI1IF) is set. This interrupt can be disabled through
an interrupt enable bit (SPI1IE).
14.2 Receive Operations
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPIxSR to SPIxBUF.
If the receive buffer is full when new data is being
transferred from SPIxSR to SPIxBUF, the module sets
the SPIROV bit, indicating an overflow condition. The
transfer of the data from SPIxSR to SPIxBUF is not
completed, and the new data is lost. The module will
not respond to SCL transitions while SPIROV is ‘1’,
effectively disabling the module until SPIxBUF is read
by user software.
14.3 Transmit Operations
Transmit writes are also double-buffered. The user
application writes to SPIxBUF. When the Master or
Slave transfer is completed, the contents of the shift
register (SPIxSR) are moved to the receive buffer. If any
transmit data has been written to the buffer register, the
contents of the transmit buffer are moved to SPIxSR.
The received data is thus placed in SPIxBUF and the
transmit data in SPIxSR is ready for the next transfer.
Note:
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register.
14.4 SPI Setup
To set up the SPI module for the Master mode of
operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSn
register.
b) Set the SPIxIE bit in the respective IECn
register.
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON
register with MSTEN (SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start as
soon as data is written to the SPIxBUF register.
To set up the SPI module for the Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSn
register.
b) Set the SPIxIE bit in the respective IECn
register.
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then set the SSEN bit
(SPIxCON1<7>) to enable the SSx pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
The SPI module generates an interrupt indicating
completion of a byte or word transfer, as well as a
separate interrupt for all SPI error conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 125